Stt mram magnetic tunnel junction architecture and integration

ABSTRACT

A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/355,941 entitled “STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE ANDINTEGRATION” by Seung H. Kang, et al., filed on Jan. 19, 2009, whichclaims the benefit of U.S. Provisional Patent Application No.61/046,520, entitled “STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE ANDINTEGRATION” by Seung H. Kang, et al., filed on Apr. 21, 2008, thedisclosures of which are expressly incorporated by reference herein intheir entireties.

TECHNICAL FIELD

This disclosure relates to integrated electronic circuitry, and inparticular, to magnetic random access memory (MRAM) and methods ofintegration with standard integrated circuitry.

BACKGROUND

Unlike conventional random access memory (RAM) chip technologies, inmagnetic RAM (MRAM) data is not stored as electric charge, but isinstead stored by magnetic polarization of storage elements. Theelements are formed from two magnetically polarized plates, each ofwhich can maintain a magnetic polarization field, separated by a thininsulating layer, which together form a magnetic tunnel junction (MTJ).One of the two plates is a permanent magnet (hereinafter “fixed layer”)set to a particular polarity; the polarization of the other plate(hereinafter “free magnetization layer” or “free layer”) will change tomatch that of a sufficiently strong external field. A memory device maybe built from a grid of such cells.

Reading the polarization state of an ;MRAM cell is accomplished bymeasuring the electrical resistance of the cell's MTJ. A particular cellis conventionally selected by powering an associated transistor thatswitches current from a supply line through the MTJ to a ground. Due tothe tunneling magnetoresistance effect, the electrical resistance of thecell changes due to the relative orientation of the polarizations in thetwo magnetic layers of the MTJ. By measuring the resulting current, theresistance inside any particular cell can be determined, and from thisthe polarity of the free writable layer determined. If the two layershave the same polarization, this is considered to mean State “0”, andthe resistance is “low,” while if the two layers are of oppositepolarization the resistance will be higher and this means State “1”.

Data is written to the cells using a variety of techniques. Inconventional MRAM, an external magnetic field is provided by current ina wire in proximity to the cell, which is strong enough to align thefree layer. Spin-transfer-torque (STT) MRAM uses spin-aligned(“polarized”) electrons to directly torque the domains of the freelayer. Specifically, such polarized electrons flowing into the freelayer by exerting a sufficient torque to realign (e.g., reverse) themagnetization of the free layer

One significant determinant of a memory system's cost is the density ofthe components. Smaller components, and fewer components for each cell,enable more cells to be packed onto a single chip, which in turn meansmore chips can be produced at once from a single semiconductor wafer andfabricated at lower cost and improved yield. Scaling integrated circuitsto higher device pitch density, however, increases the demands on thecritical dimensions of mask registration in fabricating the multiplelayers of such devices.

In addition, the manufacturing process flow impacts cost. Theconventional processes to fabricate MRAM are complex, requiring a numberof masks dedicated solely to the fabrication of the magnetic tunneljunction (MTJ) structure. There is a need, therefore, for improvedmethods for MRAM fabrication, especially if the fabrication processescould be integrated into the conventional semiconductor BEOL(back-end-of-line) process flow with relaxed mask registrationrequirements.

SUMMARY

A magnetic random access memory (MRAM) device and method of integratingfabrication processes of the MRAM device into standard back-end-of-line(BEOL) integrated circuit manufacturing is disclosed.

In an aspect, a magnetic tunnel junction (MTJ) device for a magneticrandom access memory (MRAM) device includes a substrate having a firstmetal interconnect and a first dielectric passivation barrier layerformed on the substrate. The first dielectric passivation barrier layerhas a first contact via formed with a first mask pattern to expose thefirst metal interconnect. The device also includes a first electrodelayer formed on the first dielectric passivation barrier layer and thefirst contact via, a fixed magnetization layer formed on the firstelectrode layer, a tunnel barrier layer formed on the fixedmagnetization layer, and a free magnetization layer formed on the tunnelbarrier layer. The first electrode layer is in communication with thefirst metal interconnect. The device also includes a second electrodelayer formed on the free magnetization layer. At least the secondelectrode layer and the free magnetization layer have a shape based upona second mask pattern and are located over the first contact via. Thedevice further includes a second dielectric passivation barrier layerformed on the fixed magnetization layer and around the tunnel barrierlayer, the free magnetization layer and the second electrode layer. Thesecond dielectric passivation barrier layer only partially covers thesecond electrode layer. The second dielectric passivation barrier layerand at least a first portion of the fixed magnetization layer have ashape based upon a third mask pattern.

In another aspect, a method for integrating a magnetic tunnel junction(MTJ) device into an integrated circuit includes providing in asemiconductor back-end-of-line (BEOL) process flow a substrate having afirst interlevel dielectric layer and a first metal interconnect. Themethod includes depositing on the substrate a first dielectricpassivation barrier layer having a first contact via formed with a firstmask pattern to expose the first metal interconnect. The method furtherincludes depositing over the first interlevel dielectric layer, thefirst metal interconnect and the first dielectric passivation barrierlayer, a first electrode layer in communication with the first metalinterconnect, a fixed magnetization layer on the first electrode layer,a tunnel barrier layer on the fixed magnetization layer, a freemagnetization layer on the tunnel barrier layer, and a second electrodelayer on the free magnetization layer. The method still further includespatterning an MTJ stack, over the first contact via, with a second maskpattern, in which the MTJ stack includes the free magnetization layerand the second electrode layer. The method also includes depositing asecond dielectric passivation barrier layer around the MTJ stack. Thesecond dielectric passivation bather layer is formed to leave the secondelectrode layer exposed. The method also includes depositing a thirdelectrode layer on the second dielectric passivation barrier layercommunication with the second electrode layer. The method furtherincludes pattern the first electrode layer, at least a portion of thefixed magnetization layer, and the second dielectric passivation barrierlayer with a third mask pattern.

In yet another aspect, a magnetic tunnel junction (MTJ) structure formagnetic random access memory (MRAM) has a first interconnect means forcommunicating with at least one control device. The structure also has afirst electrode means for coupling to the first interconnect meansthrough a contact via formed in a dielectric passivation barrier using afirst mask. The structure includes an MTJ means for storing data, theMTJ means coupling to the first electrode means. A lateral dimension ofa portion of the MTJ means is defined by a second mask. The structurealso has a second electrode means for coupling to the MTJ means, thesecond electrode means having a same lateral dimension as the portion ofthe MTJ means defined by the second mask. The structure has a thirdelectrode means and a second interconnect means. The third electrodemeans is for coupling to the second electrode means. The third electrodemeans, a portion of the MTJ means and the first electrode means have ashape based upon a third mask. The second interconnect means is forcoupling to the third electrode means and at least one other controldevice.

The foregoing has outlined rather broadly the features and technicaladvantages of the present disclosure in order that the detaileddescription of the embodiments that follow may be better understood.Additional features and advantages of the embodiments will be describedhereinafter which form the subject of the claims of the disclosure. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiments disclosed may be readily utilized as a basisfor modifying or designing other structures for carrying out the samepurposes of the present disclosure. It should also be realized by thoseskilled in the art that such equivalent constructions do not depart fromthe spirit and scope of the disclosure as set forth in the appendedclaims. The novel features which are believed to be characteristic ofthe disclosure, both as to its organization and method of operation,together with further objects and advantages will be better understoodfrom the following description when considered in connection with theaccompanying figures. It is to be expressly understood, however, thateach of the figures is provided for the purpose of illustration anddescription only and is not intended as a definition of the limits ofthe present embodiments of the disclosure.

DESCRIPTION OF THE FIGURES

For a more complete understanding of the present disclosure, referenceis now made to the following descriptions taken in conjunction with theaccompanying drawings.

FIG. 1 is a block diagram showing an exemplary wireless communicationsystem in which embodiments of the disclosure may be advantageouslyemployed.

FIG. 2 is a block diagram illustrating a design workstation used forcircuit, layout, logic design and integration of MRAM in a semiconductorback-end-of-line (BEOL) process flow, in accordance with an embodimentof the disclosure.

FIG. 3 is a block diagram showing a prior art implementation of an MTJstructure.

FIG. 4 is a block diagram showing an exemplary MTJ structure, inaccordance with an embodiment of the disclosure.

FIG. 5 is a schematic illustration of an exemplary process of formingthe embodiment of the MTJ structure shown in FIG. 4.

DETAILED DESCRIPTION

Disclosed is an architecture for magnetic RAM (MRAM) devices and methodsof integration with standard semiconductor circuit back-end-of-line(BEOL) fabrication processes. In one embodiment, the MTJ and method offorming disclosed pertain to conventional MRAM. In another embodiment, aspin-torque-transfer (STT) MRAM is disclosed.

FIG. 1 shows an exemplary wireless communication system 100 in which anembodiment of the disclosure may be advantageously employed. Forpurposes of illustration, FIG. 1 shows three remote units 120, 130, and150 and two base stations 140. It will be recognized that conventionalwireless communication systems may have many more remote units and basestations. Remote units 120, 130, and 150 include MRAM and/or STT MRAMmemory devices 125A, 125B and 125C, which are embodiments of thedisclosure as discussed further below. FIG. 1 shows forward link signals180 from the base stations 110 and the remote units 120, 130, and 150and reverse link signals 190 from the remote units 120, 130, and 150 tobase stations 140.

In FIG. 1, the remote unit 120 is shown as a mobile telephone, theremote unit 130 is shown as a portable computer, and the remote unit 150is shown as a fixed location remote unit in a wireless local loopsystem. For example, the remote units may be mobile phones, hand-heldpersonal communication systems (PCS) units, portable data units such aspersonal data assistants, navigation devices (such as GPS enableddevices), set top boxes, music players, video players, entertainmentunits, fixed location data units such as meter reading equipment, or anyother device that stores or retrieves data or computer instructions, orany combination thereof. Although FIG. 1 illustrates remote unitsaccording to the teachings of the disclosure, the disclosure is notlimited to these exemplary illustrated units. The disclosed device maybe suitably employed in any device which includes MRAM devices.

FIG. 2 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of the disclosed semiconductorintegrated circuit. A design workstation 200 includes a hard disk 201containing operating system software, support files, and design softwaresuch as CADENCE or ORCAD. The design workstation 200 also includes adisplay 202 to facilitate design of a circuit design 210. The circuitdesign 210 may be the memory circuit as disclosed above. A storagemedium 204 is provided for tangibly storing the circuit design 210. Thecircuit design 210 may be stored on the storage medium 204 in a fileformat such as GDSII or GERBER. The storage medium 204 may be a CD-ROM,DVD, hard disk, flash memory, or other appropriate device. Furthermore,the design workstation 200 includes a drive apparatus 203 for acceptinginput from or writing output to the storage medium 204.

Data recorded on the storage medium 204 may specify logic circuitconfigurations, pattern data for photolithography masks, or mask patterndata for serial write tools such as electron beam lithography. The datamay further include logic verification data such as timing diagrams ornet circuits associated with logic simulations. Providing data on thestorage medium 204 facilitates the design of the circuit design 210 bydecreasing the number of processes for designing semiconductor ICs.

To illustrate fabrication issues in conventional MTJ structures, FIG. 3shows an implementation of an MTJ device 300 as may be conventionallyfabricated. A metal interconnect 301 is formed in a via in an interleveldielectric layer, ILD 302 as part of a back end of line (BEOL) processflow. The ILD 302 separates a magnetic tunnel junction, MTJ 303, forexample, from a switching device, such as a transistor.

A dielectric barrier layer 304 is disposed on the ILD 302 with a via 305formed corresponding to the location of the metal interconnect 301. Thevarious layers of dielectric barriers may be formed, for example, ofmetal oxides, metal carbides, or metal nitrides. For example, thebarrier materials may be SiO_(x), SiC, SiN. The choice may be madebased, for example, on the requirement to be susceptible to or resistantto various etchants. The via 305 corresponding to the location of themetal interconnect 301 is formed using a first mask. A metallization toform a first electrode 306 may be disposed in the via 305 to contact themetal interconnect 301.

A stack of layers forming the MTJ 303 are deposited on the firstelectrode 306. The stack of layers includes a reference layer 307 (whichmay be a fixed layer and antiferro-magnet layer, not shownindividually), a tunnel barrier layer 308, and a free layer 309. Asecond electrode 310 is provided on the free layer 309. The MTJ 303 andsecond electrode 310 will be collectively referred to as the MTJ stack.A second (“stack”) mask and a series of etches create the MTJ stack asshown in FIG. 3. A dielectric passivation barrier layer 311 encapsulatesthe MTJ 303 stack, after which a planarization may be applied to levelthe dielectric passivation barrier layer 311 and expose the secondelectrode 310.

A third metallization layer to form a third electrode 312 may bedisposed over the planarized dielectric passivation barrier layer 311,making electrical contact with the second electrode 310. Metallizationsto form the first, second and third electrodes 306, 310 and 312 may beselected from various metals, including refractory-metals such astantalum (Ta). Tantalum is commonly applied to the standard BEOL due toits desirable characteristics as a diffusion barrier.

A dielectric barrier layer 313 is disposed over the third electrode 312.A third mask is then applied to pattern and define the lateral extent ofthe dielectric barrier layer 313, the third electrode 312, thedielectric passivation barrier layer 311, and the first electrode 306,as shown in FIG. 3.

Additional processes may include standard back-end-of-line (BEOL)processes. For example, a further dielectric layer (as a passivation oran ILD layer) 314 may be deposited on the dielectric barrier layer 313and the dielectric barrier layer 304. A via is formed in the dielectricbarrier layer 313 and the dielectric layer 314. The via is filled with ametal to provide a metal interconnect 315 to contact the third electrode312, as shown in FIG. 3.

Several problems may occur with the prior art structure described abovewith respect to FIG. 3. The first mask needs to be critically alignedwith the metal interconnect 301 to insure the first electrode 306contacts the metal interconnect 301. The stack mask—to define the MTJstack also needs to be critically aligned, to avoid placement of the MTJstack near the metal interconnect 301 and the corresponding via 305(formed by the first mask), and to insure proper definition andregistration of the layers of the MTJ stack. A succession of criticaldimension alignments from one mask to the next may exceed tolerances andhave an adverse effect on yield, and thus cost,

Furthermore, the dielectric barrier layer 304 may be comparable to orthicker than the first electrode 306. Thus, step coverage of the firstelectrode 306 may not be satisfactory due to topographical variation inthe vicinity near the via 305. In other words, electrical contactbetween the first electrode 306 and the metal interconnect 301 may beinadequate. Therefore, fabrication of the MTJ stack close to the edgesof the via 305 should be avoided to assure that all layers of the MTJ303 are uniform in thickness and flat when deposited. Otherwise thequality and reliability of the MTJ 303 may be adversely compromised. Itmay occur that some layers of the MTJ 303 are on the order of 1 nm, suchas the barrier layer 308, which is fragile and quite sensitive totopography. Increasing the lateral separation between the MTJ 303 andthe via 305 to isolate the MTJ 303 from the topography of the via 305and to ensure flatness may, however, undesirably require more substratespace. Equally important, the additional current path distance throughthe first electrode 306 from the MTJ 303 to the metal interconnect 301will increase contact resistance, due at least to sheet resistivity ofthe first electrode 306.

In spin torque transfer (STT) MRAM the magnetization of the free layer309 is directly modulated in write mode by electrical current flowingthrough the junction, i.e., between the reference layer 307 and the freelayer 309 by tunneling through the barrier layer 308. Depending on howelectrons flow, State 0 or State 1 may be written because the electroncurrent is spin polarized, which sets the free layer polarization. Aswith conventional MRAM the electrical current of the device junction isdetermined in read mode by determining the electron tunneling resistancethrough the barrier layer 308 between two magnetic layers the referencelayer 307 and the free layer 309, whose relative polarizations may beparallel or anti-parallel

FIG. 4 illustrates an MTJ device 400 according to one embodiment of thedisclosure. In this embodiment (as described in more detail below) onlyone mask defines critical selected nano-scale features of the MTJstructure, but the mask alignment is not a critical dimension. Theremaining masks and associated processes benefit from relaxed criticaldimension requirements. The process is integration compatible with asemiconductor back-end-of-line (BEOL) process flow. Furthermore, cellscaling to smaller MTJ size may result in faster switching speed, higherdrive current densities, lower absolute current and power, improvedstability of the MTJ reference stack layers, and reduced stray magneticfield effects. The MTJ device 400 is implemented in STT MRAM although itmay alternatively be applicable for conventional MRAM.

In one embodiment of the disclosure, the MTJ fabrication portion of theentire device fabrication process (i.e., including bothfront-end-of-line (FEOL) and back-end-of-line (BEOL) processes) isstructured to allow inclusion of a process flow for formation of atleast a nano-scale portion of the MTJ device (including at least asecond electrode layer 410, a free layer 409, and a tunnel barrier layer408, described in detail below). This portion of the additional processflow uses only one mask that is critical as to feature size. The onemask is not sensitive to placement alignment. A second portion of theadditional process flow uses two masks that contain larger structuralelements of the MTJ device (i.e., the reference layer 407 (which may bea fixed antiferromagnet layer and a synthetic antiferromagnet (SAF)layer, not shown individually), a first electrode 406, and a thirdelectrode 412, also described in detail below), where the mask alignmentis relatively non-critical. Thus, a method of integrating an MRAM MTJinto the BEOL process flow for fabrication of integrated circuitry isprovided where one device size critical dimension mask and twoadditional masks where placement alignment is relatively non-criticalare employed.

A first mask opens a first contact via (also referred to as a seedopening) 405 in a dielectric barrier layer 404 to expose a metalinterconnect 401 in a sub-layer, where the contact via opening may besubstantially larger than the metal interconnect 401. The mask allowsfor the large contact via opening to provide a large planar area toeasily position the smaller MTJ structure in subsequent fabricationprocesses, thereby relaxing critical alignment registration, andimproving the uniformity and stability of the to be deposited referencemagnetization layer 407. A first electrode 406, larger than the contactvia 405, is formed with another mask (also referred to as the “third”mask), thus insuring overlap and contact with the metal interconnect 401and to circuitry previously formed, i.e., beneath the MTJ device 400,and overlapping the surrounding rim of the contact via 405 (formed bythe dielectric barrier layer 404) without requiring critical maskalignment.

The reference layer 407 may he patterned using the same mask as used toform the first electrode 406. The reference layer 407 and firstelectrode 406 are larger than the nano-scale portion of the MTJ. Thelarger reference layer 407 and contact via area ensure greater stabilityof the fixed magnetic reference field over the lifetime of the device,and places the fringing fields at the edges of the reference layer 407farther from the free layer 409 of the nano-scale portion of the MTJ toreduce the stray field effect.

Two advantages accrue: alignment of the first electrode 406 to connectto the metal interconnect 401 is thus a non-critical alignment, andplacement of the nano-scale MTJ portion on the reference layer 407 isnon-critical, provided the nano-scale MTJ portion is placed away fromany topographical feature, such as the edge associated with the overlapof the reference layer/first electrode 407/406 near the rim of thebarrier layer contact via 405. When the metal interconnect formationprocess require planarization, the nano-scale MTJ portion may bepositioned to avoid this area as well.

The nano-scale portion of the MTJ includes a tunnel barrier layer 408and a free layer 409, referred to as a “stack.” The stack may furtherinclude a second electrode 410 in contact with the free layer 409,opposite the tunnel barrier layer 408. The stack is patterned and etchedusing a second mask. In another embodiment, the tunnel barrier layer 408is formed using the third mask, thereby making the tunnel barrier layer408 substantially the same in surface area and shape as the referencelayer 407 and the first electrode 406.

A third electrode 412 may be patterned with the same third mask used forpatterning the reference layer 407 and the first electrode 406, which isagain a non-critical alignment.

The contact via 405 is formed in the dielectric barrier 404, and isdefined by a first mask pattern. The contact via 405 is larger than thevia 305 formed in the conventional structure shown in FIG. 3. The firstelectrode 406 is formed over a first interlayer dielectric (ILD) 402,the dielectric barrier 404, and the metal interconnect 401, overlappingthe edge of the large contact via 405. That is, the first electrode 406overlaps the rim of the dielectric barrier 404 that forms the boundaryof the contact via 405. Positioning the contact via 405 over the metalinterconnect 401 is not sensitive to location with respect to the metalinterconnect 401, in contrast to the example of the via 305 and metalinterconnect 301 shown in FIG. 3. Therefore, placement accuracy of thefirst mask to form the contact via 405 is not a critical dimension,improving the reliability and yield of this process.

The various layers of dielectric barriers included in the structure,such as the dielectric barrier 404, may be formed, for example, of metaloxides, metal carbides, or metal nitrides. For example, the barriermaterials may be SiO_(x), SiC, SiN. The choice may be made based on thedesirability of being susceptible to or resisting various etchants.

The reference layer 407 is deposited aver the metallization from whichthe first electrode 406 is formed before any patterning occurs.Additionally, the tunnel barrier layer 408, free layer 409, and(optionally) a metal layer for the second electrode 410 may be formedover the reference layer 407, successively. The layers 408, 409, 410 maybe patterned in a single process with a second mask, and the layerssuccessively etched appropriately to form the MTJ “stack.” Whereas thedimensions of the stack may be nano-scale, and have a criticaldimension, placement of the mask is not a critical dimension. Providedthe area of the contact via 405 has been chosen to be appropriatelylarge, the stack can be formed within and away from the stepped edges ofthe first electrode 406 and the reference layer 407 at the rim of viacontact via 405. The stack may also be positioned over the location ofthe metal interconnect 401 if dishing in the metal interconnect 401 isnot significant.

As an example of dimensions appropriate for an exemplary STT MRAM MTJ,for 65 nm and 45 nm technology nodes, the metal interconnect 401 may beon the order of 70 nm. The first electrode 406 and reference layer 407my have dimensions where the planar portion defined by the via contactvia 405 are at least 70 mm. The cell size of the MRAM may be affected bythe size of the first electrode 406 or the third electrode 412.Therefore, the contact via 405 may be larger than the via 305. Thecritical dimension registration is further relaxed, as long asconductive contact exists between the first electrode 406 and the metalinterconnect 401.

The MTJ device 400 includes a second (local) dielectric passivationbarrier layer 411 to isolate the stack, and a third electrode layer 412.The third mask, which is non-critical in alignment and is larger thanthe contact via 405, patterns the MTJ structure from the third electrodelayer 412 down to the first electrode 406. The MTJ device 400 alsoincludes a global dielectric passivation barrier layer 416 toencapsulate the layers previously formed and etched. The globaldielectric passivation barrier layer 416 inhibits contaminantpenetration into (or from) the critical layers of the junction,including the electrodes 406, 410, 412, the fixed reference layer 407,the free layer 409, and the tunnel barrier layer 408.

The MTJ device 400 is completed with subsequent processes that maysubstantially be a BEOL process flow, e.g., to planarize the structureand provide electrical connectivity to other circuitry, with, forexample a metal interconnect 415. It may be appreciated that metalinterconnects 401 and 415 may be applied as source and bit lines.

FIG. 5 illustrates an exemplary process 500 for forming of the MTJdevice 400 according to one embodiment. Process 1 is the point at whichthe method of forming the MTJ device 400 is inserted into the standardBEOL process flow, and process 8 is the point at which the conventionalBEOL process flow continues.

Process 1: A substrate comprising the ILD 402 with a through hole viacontaining the metal interconnect 401, is over coated with the firstdielectric passivation barrier layer 404. A first mask pattern opens thecontact via 405 of a selected size, at least overlapping and larger thanthe metal interconnect 401. Then the substrate is over-coated with asuccession of layers: an electrode layer metallization for the firstelectrode 406, the magnetization reference layer 407, the tunnel barrierlayer 408, the free layer 409, and a second metallization layer for thesecond electrode 410.

Process 2: A second mask pattern (“stack” mask), defines the critical(or nano scale) portion of the MTJ device. In one embodiment, the sizeof the critical portion is smaller than the contact via 405. In thisembodiment, the second electrode 410, the free layer 409 and the tunnelbarrier layer 408 are patterned based upon the second mask. As only afew layers are etched and a relatively thinner portion of the MTJ isprocessed, this etching process is easier to control, e.g., with respectto undercutting, over-etching etc., and the process is inherentlyself-aligned. In this embodiment, the tunnel barrier layer 408 ispatterned with the second mask pattern. In another embodiment (notshown), the tunnel barrier layer 408 is patterned with a third maskpattern, as described in Process 6. The second mask may be configured topattern the critical portion in the shape of an ellipse to enhance thepolarization alignment/anti-alignment between the free layer 409 and themagnetization reference layer 407 in the two polarization states. In oneembodiment, a portion of the reference layer 407 is etched during thesecond mask process. For example all or a portion of the SAF layer maybe etched. If all of the synthetic antiferromagnet (SAF) layer isetched, a small portion of the fixed antiferromagnet layer may also beetched.

Process 3: After the critical portion of MTJ device 400 is defined, thesecond dielectric passivation barrier layer 411 is deposited to insulateand encapsulate the critical portion. The second dielectric passivationbarrier layer 411 may commonly be silicon nitride, silicon oxide oranother dielectric material. It can be the same material as thedielectric passivation barrier layer 404, or another insulatingmaterial, depending on characteristics of other fabrication processes.

Process 4: The deposited second dielectric passivation barrier 411surface is planarized to expose the second electrode 410.

Process 5: Because the dimensions of the second electrode 410 may besmall, i.e., nano-scale, an additional metallization is deposited on thesurface of the substrate to be later patterned to form the thirdelectrode 412. The third electrode 412 contacts the second electrode410.

Process 6: A third mask process patterns a cell of the MTJ device 400,from the third electrode 412 down to the first electrode 406, andincluding the second dielectric passivation barrier 411. A series ofmaterial selective etches may be applied to provide the net cell shape(as determined by the third mask) from the third electrode 412vertically down to, but not including, the dielectric barrier layer 404.Although FIG. 4 shows the same mask process for patterning the thirdelectrode 412, a different mask may be optionally used to form a thirdelectrode with a different shape and size, if desired.

Process 7: A global dielectric passivation barrier layer 416 is thendeposited over the entire exposed surface, to further “cap” thestructure formed in Process 6. The global dielectric passivation barrierlayer 416 can be the same material as the dielectric barrier layer 404,or it can be different. Exemplary materials include silicon carbide,silicon nitride, silicon oxide, and a combination thereof.

Process 8: A second interlayer dielectric (ILD) 414 is deposited overthe global dielectric passivation barrier layer 416 and planarized, ifdeposited with an over-burden, to expose a portion of the passivationbarrier layer 416 directly over the nano scale MTJ structure. Theplanarized ILD 414 may serve as a substrate upon which to buildadditional levels of device functionality within the BEOL process flow.The same mask (i.e., the second mask) used to pattern the MTJ stack, oranother mask, may optionally be used to pattern a contact via in thedielectric passivation barrier layer 416 formed in Process 7.Alternatively, another BEOL specified mask may be used. The contact viapermits formation of the metal interconnect 415. The mask registrationis not critical, and need not be placed directly over the MTJ stack.However, contact resistance my be reduced by such direct placement.

It may be appreciated that the structure and method disclosed are“manufacture friendly,” in that only one of the three masks is used todefine critical dimension elements. Moreover, alignment registration ofthe three masks is not a critical dimension requirement. In addition, itbecomes easier to control the polarization of the free layer duringmemory operation because of a much larger reference layer, whichprovides a more uniform fixed magnetization field.

A further advantage is improved scalability: fabrication of smaller MTJstructures for the critical free layer portion permits higher drivecurrent density (with lower absolute current) resulting in fasterswitching, while stability is improved by the larger reference layer.

A still further advantage is the improved yield, because the method isless susceptible to process induced defects and damage that mayotherwise occur where critical dimension registration among a greaternumber of masks is required.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the spirit andscope of the disclosure as defined by the appended claims. For example,although a read operation has been used in the discussion, it isenvisioned that the disclosure equally applies to write operations.Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, and methods described in thespecification. As one of ordinary skill in the art will readilyappreciate from the embodiments of the present disclosure, processes,machines, manufacture, compositions of matter, means, and methods,presently existing or later to be developed that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present disclosure. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, and methods.

What is claimed is:
 1. A method for integrating a magnetic tunneljunction (MTJ) device into an integrated circuit comprising: providingin a semiconductor back-end-of-line (BEOL) process flow a substratehaving a first interlevel dielectric layer and a first conductiveinterconnect; depositing on the substrate a first dielectric passivationbarrier layer having a first contact via opening formed with a firstmask pattern to expose the first conductive interconnect: depositingover the first interlevel dielectric layer, the first conductiveinterconnect and the first dielectric passivation barrier layer, a firstelectrode layer in communication with the first conductive interconnect,a fixed magnetization layer on the first electrode layer, a tunnelbarrier layer on the fixed magnetization layer, a free magnetizationlayer on the tunnel barrier layer, and a second electrode layer on thefree magnetization layer; patterning an MTJ stack, over the firstcontact via opening, with a second mask pattern, in which the MTJ stackcomprises the free magnetization layer and the second electrode layer;depositing a second dielectric passivation barrier layer around the MTJstack, in which the second dielectric passivation barrier layer isformed to leave the second electrode layer exposed; depositing a thirdelectrode layer on the second dielectric passivation barrier layer incommunication with the second electrode layer; and patterning the firstelectrode layer, at least a portion of the fixed magnetization layer,and the second dielectric passivation barrier layer with a third maskpattern.
 2. The method of claim 1, in which patterning the MTJ stackfurther includes patterning the tunnel barrier layer with the secondmask pattern.
 3. The method of claim 1, further comprising patterningthe tunnel barrier layer with the third mask pattern.
 4. The method ofclaim 1, further comprising patterning the third electrode layer withthe third mask pattern.
 5. The method of claim 1, further comprisingfabricating a second conductive interconnect in communication with thethird electrode layer.
 6. The method of claim 1, further comprisingdepositing a global dielectric passivation barrier layer over the thirdelectrode layer after patterning with the third mask pattern.
 7. Themethod of claim 6, further comprising: depositing a second interlayerdielectric on the global dielectric passivation barrier layer;planarizing the second interlayer dielectric to expose the globaldielectric passivation barrier layer over the third electrode layer; andforming a second contact via opening in the global dielectricpassivation barrier layer to expose a portion of the third electrodelayer.
 8. The method of claim 1, further comprising patterning a secondportion of the fixed magnetization layer with the second mask pattern,9. The method of claim 1, in which the second mask pattern has anellipsoid shape
 10. The method of claim 1, further comprisingintegrating the MTJ device into a spin torque transfer (STT) magneticrandom access memory (MRAM) device.
 11. The method of claim 1, furthercomprising integrating the MTJ device into a semiconductor device. 12.The method of claim 1, wherein the integrated circuit is applied in anelectronic device, selected from a group consisting of a set top box,music player, video player, entertainment unit, navigation device,communications device, personal digital assistant (PDA), fixed locationdata unit, and a computer, into which the integrated circuit isintegrated.
 13. A magnetic tunnel junction (MTJ) structure for magneticrandom access memory (MRAM) comprising: first interconnect means forcommunicating with at least one control device; first electrode meansfor coupling to the first interconnect means through a contact viaopening formed in a dielectric passivation barrier using a first mask;means for magnetically storing data, the storing means coupling to thefirst electrode means, a lateral dimension of a portion of the storingmeans being defined by a second mask; second electrode means forcoupling to the storing means, the second electrode means having a samelateral dimension as the portion of the storing means defined by thesecond mask; third electrode means for coupling to the second electrodemeans, the third electrode means, a portion of the storing means and thefirst electrode means having a shape based upon a third mask; and secondinterconnect means for coupling to the third electrode means and atleast one other control device.
 14. The MTJ structure of claim 13, inwhich the contact via opening is at least as wide as the firstinterconnect means.
 15. The MTJ structure of claim 13, in which thesecond mask has an ellipsoid shape.
 16. The MTJ structure of claim 13,in which a tunnel barrier layer shape of the storing means is based uponthe second mask.
 17. The MTJ structure of claim 13, integrated into aspin-torque-transfer (STT) MRAM semiconductor die.
 18. The MTJ structureof claim 13, in which the MTJ structure is integrated into a deviceselected from a group consisting of a set top box, music player, videoplayer, entertainment unit, navigation device, communications device,personal digital assistant (PDA), fixed location data unit, and acomputer.
 19. A method for integrating a magnetic tunnel junction (MTJ)device into an integrated circuit comprising the steps of: providing ina semiconductor back-end-of-line (BEOL) process flow a substrate havinga first interlevel dielectric layer and a first conductive interconnect;depositing on the substrate a first dielectric passivation barrier layerhaving a first contact via opening formed with a first mask pattern toexpose the first conductive interconnect: depositing over the firstinterlevel dielectric layer, the first conductive interconnect and thefirst dielectric passivation harrier layer, a first electrode layer ncommunication with the first conductive interconnect, a fixedmagnetization layer on the first electrode layer, a tunnel barrier layeron the fixed magnetization layer, a free magnetization layer on thetunnel barrier layer, and a second electrode layer on the fleemagnetization layer; patterning an MTJ stack, over the first contact viaopening, with a second mask pattern, in which the MTJ stack comprisesthe free magnetization layer and the second electrode layer; depositinga second dielectric passivation barrier layer around the MTJ stack, inwhich the second dielectric passivation barrier layer is formed to leavethe second electrode layer exposed; depositing a third electrode layeron the second dielectric passivation barrier layer in communication withthe second electrode: layer; and patterning the first electrode layer,at least a portion of the fixed magnetization layer and the seconddielectric passivation barrier layer with a third mask pattern.
 20. Themethod of claim 19, wherein the integrated circuit is applied in anelectronic device, selected from a group consisting of a set top box,music player, video player, entertainment unit, navigation device,communications device, personal digital assistant (PDA), fixed locationdata unit, and a computer, into which the integrated circuit isintegrated.